//------------------------------------------------------------
//  Filename: tcdm_lint_connect.sv
//   
//  Author  : wlduan@ucchip.com
//  Revise  : 2019-10-16 15:51
//  Description: 
//   
//  Copyright (C) 2019, UCCHIP, Inc. 					      
//  All Rights Reserved.                                       
//-------------------------------------------------------------
//

`timescale 1ns/1ps 

module tcdm_lint_mem #(
    parameter DATA_WIDTH = 32,
    parameter ADDR_WIDTH = 32
)(
    input  logic   clk,
    input  logic   rst_n,

	LINT_IF.Slave   lint_slave ,
	MEMBK_IF.Master mmbk_master
);
//-------------------------------------------------------
logic r_valid;
//-------------------------------------------------------
always @(posedge clk,negedge rst_n) begin
    if(rst_n == 1'b0) begin 
        r_valid <= 'b0;
    end 
    else begin 
        r_valid <= mmbk_master.mem_en;
    end 
end 
//-------------------------------------------------------
assign mmbk_master.mem_en = lint_slave.data_req; 
assign mmbk_master.mem_addr = lint_slave.data_addr[ADDR_WIDTH-1:0]; 
assign mmbk_master.mem_we = lint_slave.data_we; 
assign mmbk_master.mem_wdata = lint_slave.data_wdata; 
assign mmbk_master.mem_be = lint_slave.data_be; 
//-------------------------------------------------------
assign lint_slave.data_gnt = mmbk_master.mem_en; 
assign lint_slave.data_r_rdata = mmbk_master.mem_rdata; 
assign lint_slave.data_r_valid = r_valid; 
assign lint_slave.data_r_opc = 'b0; 

endmodule  
